Magnetic random access memory (MRAM) that incorporates a magnetic tunnel junction (MTJ) as a memory storage device is a strong candidate to provide a high density, fast (1–30 ns read/write speed), low power, and non-volatile solution for future memory applications. The architecture for MRAM devices is composed of an array of memory cells generally arranged in rows and columns. Each memory cell is comprised of a memory element (MTJ) that is in electrical communication with a transistor through an interconnect stack. The memory elements are programmed by a magnetic field created from pulse current carrying conductors such as copper lines. Typically, two arrays of current carrying conductors that may be called “word lines” and “bit lines” are arranged in a cross point matrix. Normally, the word lines are formed under the MTJs and are isolated from the memory elements by a dielectric layer. The bit lines contact the top portion of the MTJs and are electrically connected to a conductive cap layer. Additionally, there is a bottom electrode that contacts the bottom of each MTJ and electrically connects the MTJ with an underlying transistor.
The MTJ consists of a stack of layers with a configuration in which two ferromagnetic layers are separated by a thin insulating layer such as AlOx that is called a tunnel barrier layer. One of the ferromagnetic layers is a pinned layer in which the magnetization (magnetic moment) direction is more or less uniform along a preset direction and is fixed by exchange coupling with an adjacent anti-ferromagnetic (AFM) pinning layer. The second ferromagnetic layer is a free layer in which the magnetization direction can be changed by external magnetic fields. The magnetization direction of the free layer may change in response to external magnetic fields which can be generated by passing currents through a bit line and word line as in a write operation. When the magnetization direction of the free layer is parallel to that of the pinned layer, there is a lower resistance for tunneling current across the insulating layer (tunnel barrier) than when the magnetization directions of the free and pinned layers are anti-parallel. The MTJ stores digital information (“0” and “1”) as a result of having one of two different magnetic states.
In a read operation, the information is read by sensing the magnetic state (resistance level) of the MTJ through a sensing current flowing through the MTJ, typically in a current perpendicular to plane (CPP) configuration. During a write operation, the information is written to the MTJ by changing the magnetic state to an appropriate one by generating external magnetic fields as a result of applying bit line and word line currents. Cells which are selectively written to are subject to magnetic fields from both a bit line and word line while adjacent cells (half-selected cells) are only exposed to a bit line or a word line field.
As the MTJ size shrinks in order to satisfy higher performance MRAM requirements, the interconnects within the MRAM structure also decrease in size to conform to electrical requirements and space restrictions for high density designs. There is also a greater demand on reliability of the MRAM device since reduced interconnect sizes usually lead to a greater chance of device failure at contact points between adjacent metal layers. For example, the junction between a bit line pad and word line pad, and the bit line contact region at a bond pad site often show very high contact resistance and reliability issues that degrade device performance. Therefore, an improved method of fabricating metal interconnects within an MRAM structure is needed, especially where a bit line pad contacts a word line pad and at bit line contacts to bond pad areas.
In U.S. Pat. No. 6,806,096, an integration scheme is disclosed whereby a buffer insulating layer is deposited over an MTJ stack and conductive hard mask to protect these elements during a damascene process that forms interconnects to first conductive lines. However, the need to improve the electrical connection between a bit line pad and word line pad is not addressed.
U.S. Pat. No. 6,709,942 and related Patent Application Publication 2003/0168684 describe a method of fabricating MRAM devices by employing a dual damascene process that involves forming a bit line that contacts a free layer in an MTJ. Again, bit line to word line contact issues are not discussed.
U.S. Pat. No. 6,912,152 discloses a method whereby read word lines are formed below an MTJ and write bit lines are disposed above the MTJ by a damascene process.